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19-2689; Rev 0; 1/03
Bus LVDS 3.3V Single Transceiver
General Description
The MAX9163 high-speed bus low-voltage differential signaling (BLVDS) transceiver is designed specifically for heavily loaded multipoint bus applications. The MAX9163 operates from a single 3.3V power supply, and is pin compatible with the DS92LV010A. The transceiver consists of one differential BLVDS line driver and one LVDS receiver. The driver output and receiver input are connected internally to minimize bus loading. The individual enable logic inputs (DE, RE) are used to enable the driver or the receiver. The MAX9163 driver output uses a current-steering configuration to generate a 9mA (typ) drive current. The driver accepts a single-ended input and translates it to a differential output level of 243mV (typ) into 27 at speeds up to 200Mbps. The MAX9163 receiver detects a differential input as low as 100mV and translates it to a single-ended output at speeds up to 200Mbps. The receiver input features a fail-safe circuit that sets the receiver output high when the receiver inputs are undriven and open, terminated, or shorted. The MAX9163 is offered in an 8-lead SO package, and is specified for operation from -40C to +85C. o BLVDS Signaling o 3.3V Operation o Low-Power CMOS Design o 200Mbps Data-Signaling Rate o 1V Common-Mode Range o 100mV Receiver Sensitivity o Flow-Through Pinout o Receiver Output High for Undriven Open, Short, or Terminated Input o 8-Lead SO Package
Features
MAX9163
Ordering Information
PART MAX9163ESA TEMP RANGE -40C to +85C PIN-PACKAGE 8 SO
Applications
Cell-Phone Base Stations Add/Drop Muxes Digital Cross-Connects DSLAMs Network Switches/Routers Backplane Interconnect Clock Distribution
DE 1 DIN 2 ROUT 3
Pin Configuration
TOP VIEW
MAX9163 8 7 6 5 VCC DO+/RI+ DO-/RIRE
GND 4
SO
Typical Application Circuit appears at end of data sheet.
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
Bus LVDS 3.3V Single Transceiver MAX9163
ABSOLUTE MAXIMUM RATINGS
VCC to GND ...........................................................-0.3V to +4.0V DO+/RI+, DO-/RI- to GND.....................................-0.3V to +4.0V DIN, ROUT, DE, RE to GND .......................-0.3V to (VCC + 0.3V) Driver Short-Circuit Current .......................................Continuous Continuous Power Dissipation (TA = +70C) 8-Pin SO (derate 5.9mW/C above +70C)..................471mW Operating Temperature Range ...........................-40C to +85C Junction Temperature ......................................................+150C Storage Temperature Range .............................-65C to +150C ESD Protection HBM (1.5k, 100pF), DO+/RI+, DO-/RI-, DIN, ROUT, DE, RE........................> 2kV Lead Temperature (soldering, 10s) .................................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
(VCC = 3.0V to 3.6V, RE = 0, |VID| = 0.1V to 2.9V, common-mode input voltage (VCM) = |VID/2| to 3.0V - |VID|/2, RL = 27 1%, TA = -40C to +85C. Typical values are at VCC = 3.3V, |VID| = 0.2V, VCM = 1.2V, TA = +25C, unless otherwise noted.) (Notes 1, 2)
PARAMETER SINGLE-ENDED INPUTS (DIN, DE, RE) Input High Voltage Input Low Voltage Input Current Input Diode Clamp Voltage DRIVER OUTPUT (DO+/RI+, DO-/RI-) Differential Output Voltage Change in Magnitude of VOD Between Complementary Output States Offset Voltage Change in Magnitude of VOS Between Complementary Output States Output Short-Circuit Current Output Capacitance RECEIVER INPUT (DO+/RI+, DO-/RI-) Differential Input High Threshold Differential Input Low Threshold Input Current RECEIVER OUTPUT (ROUT) VID = +100mV Output High Voltage VOH Inputs open Inputs shorted Inputs terminated, RL = 27 Output Low Voltage Output Short-Circuit Current VOL IOS IOL = +2.0mA, VID = -100mV, DE = low VID = +100mV, ROUT = 0, DE = low -5 0.025 -25 0.4 -85 V mA IOH = -400A, DE = Low 2.90 3.28 V VTH VTL IIN DE = low DE = low DE = low, VCC = 0 or 3.6V; DO+/RI+, DO-/RI- = 2.4V or 0; Figure 6 -100 -20 +20 100 mV mV A VOD VOD VOS VOS IOSD COUT Figure 1 Figure 1 Figure 1 Figure 1 DO+/RI+ = 0, DIN = VCC DO-/RI- = 0, DIN = 0 Capacitance from DO+/RI+ or DO-/RIto GND 1.00 180 250 0.2 1.28 1.4 -9 -9 6.9 360 25 1.65 25 -20 -20 mV mV V mV mA pF VIH VIL IIN VCL RE, DE, DIN = high or low ICLAMP = -18mA 2.0 0 -10 -1.5 VCC 0.8 +10 V V A V SYMBOL CONDITIONS MIN TYP MAX UNITS
2
_______________________________________________________________________________________
Bus LVDS 3.3V Single Transceiver MAX9163
DC ELECTRICAL CHARACTERISTICS (continued)
(VCC = 3.0V to 3.6V, RE = 0, |VID| = 0.1V to 2.9V, common-mode input voltage (VCM) = |VID/2| to 3.0V - |VID|/2, RL = 27 1%, TA = -40C to +85C. Typical values are at VCC = 3.3V, |VID| = 0.2V, VCM = 1.2V, TA = +25C, unless otherwise noted.) (Notes 1, 2)
PARAMETER SUPPLY CURRENT Supply Current Driver Supply Current Receiver Supply Current Disable Supply Current ICC ICCD ICCR ICCZ DE = VCC, RE = 0 DE = RE = VCC DE = RE = 0 DE = 0, RE = VCC 13.3 13.3 4.4 4.4 20 20 8 7.5 mA mA mA mA SYMBOL CONDITIONS MIN TYP MAX UNITS
AC ELECTRICAL CHARACTERISTICS
(VCC = 3.0V to 3.6V, |VID| = 0.2V, VCM = 1.2V, RL = 27 1%, CL = 10pF, TA = -40C to +85C. Typical values are at VCC = 3.3V, |VID| = 0.2V, VCM = 1.2V, TA = +25C, unless otherwise noted.) (Notes 3, 4, 5)
PARAMETER DRIVER, DE = RE = VCC Differential High-to-Low Propagation Delay Differential Low-to-High Propagation Delay Differential Skew | tPHLD - tPLHD | Rise Time Fall Time Disable Time High to Z Disable Time Low to Z Enable Time Z to High Enable Time Z to Low RECEIVER, DE = RE = 0 Differential High-to-Low Propagation Delay Differential Low-to-High Propagation Delay Differential Skew | tPHL - tPLH | Rise Time Fall Time Disable Time High to Z Disable Time Low to Z Enable Time Z to High Enable Time Z to Low tPHL tPLH tSKD tTLH tTHL tPHZ tPLZ tPZH tPZL Figure 4 Figure 4 Figure 4 Figure 4 Figure 4 Figure 5 Figure 5 Figure 5 Figure 5 2.0 2.0 2.0 2.0 2.5 2.5 6.4 6.0 0.4 1.0 0.4 5.0 4.4 4.6 4.3 12.0 10.0 2.0 4.0 4.0 6.0 7.0 13.0 10.0 ns ns ns ns ns ns ns ns ns tPHLD tPLHD tSKD tTLHD tTHLD tPHZ tPLZ tPZH tPZL Figure 2 Figure 2 Figure 2 Figure 2 Figure 2 Figure 3 Figure 3 Figure 3 Figure 3 0.5 0.5 2.0 1.0 1.0 1.0 3.2 3.0 0.2 0.8 0.6 2.2 2.2 3.2 3.2 5.0 5.0 1.0 2.0 2.0 9.0 10.0 7.0 9.0 ns ns ns ns ns ns ns ns ns SYMBOL CONDITIONS MIN TYP MAX UNITS
Note 1: Maximum and minimum limits over temperature are guaranteed by design and characterization. Devices are 100% tested at TA = +25C. Note 2: Current into a pin is defined as positive. Current out of a pin is defined as negative. All voltages are referenced to device ground except VTH, VTL, VID, VOD, and VOD. Note 3: CL includes probe and jig capacitance. Note 4: AC parameters are guaranteed by design and characterization. Note 5: Generator waveforms for all tests unless otherwise specified: f = 100MHz, Z0 = 50, tR = tF = 6.0ns (0 to 3V, 0% to 100%) for DE and RE, tR = tF = 3.0ns (0 to 3V, 0% to 100%) for DIN, and tR = tF = 1.0ns (|VID| = 0.2V, 20% to 80%) for DO+/RI+ and DO-/RI- inputs.
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3
Bus LVDS 3.3V Single Transceiver MAX9163
Test Circuits/Timing Diagrams
DO+/RI+ RL/2 2.0V 0.8V RL/2 DO-/RIDIN VOS VOD
Figure 1. Differential Driver DC Test Circuit
CL PULSE GENERATOR 50 DIN DO+/RI+ RL DO-/RICL 3V 1.5V DIN tPLHD DO-/RI0V DO+/RI+ DO-/RI- (DIN = H) DO+/RI+ (DIN = L) tPLZ 50% 0V tPHLD DO-/RI- (DIN = L) DO+/RI+ (DIN = H) 1.5V 0V DE 1.5V tPHZ 50% PULSE GENERATOR DE 50 2V 0.8V DIN
CL RL/2 RL/2
DO+/RI+
CL
1.2V DO-/RI-
3V 1.5V 0V tPZH 50% tPZL 50% VOH 1.2V 1.2V VOL
80%
VOD
80% 0V (DIFFERENTIAL)
[DO+/RI+] [DO-/RI-]
20% tTLHD tTHLD
20%
Figure 3. Driver High-Impedance Delay Test Circuit and Waveforms
Figure 2. Driver Differential Propagation Delay and Transition Time Test Circuit and Waveforms
4
_______________________________________________________________________________________
Bus LVDS 3.3V Single Transceiver
Test Circuits/Timing Diagrams (continued)
DO+/RI+ PULSE GENERATOR DO-/RICL 50 PULSE GENERATOR 50 RE ROUT DO+/RI+ D0-/RICL 500 VCC ROUT
MAX9163
50
DO-/RI0V DIFF DO+/RI+ tPLH 80% 1.5V ROUT 20% tTLH tTHL VID VCM = 1.2V tPHL 80% 1.5V 20%
1.3V 1.1V
VCC WHEN ROUT IS LOW, GND WHEN ROUT IS HIGH. 3V
VOH RE VOL V ROUT OH
1.5V tPHZ VOH - 0.5V tPLZ ROUT VOL VOL + 0.5V
1.5V 0V tPZH 50% tPZL 50% VOH GND VCC VOL
Figure 5. Receiver High-Impedance Delay Test Circuit and Waveforms Figure 4. Receiver Propagation Delay and Transition Time Test Circuit and Waveforms
Typical Operating Characteristics
(VCC = 3.3V, FREQ = 100MHz, VID = 0.2V, VCM = 1.2V, RL = 27 1%, CL = 10pF, TA = +25C, unless otherwise noted.)
DRIVER DIFFERENTIAL OUTPUT SHORT-CIRCUIT CURRENT vs. SUPPLY VOLTAGE
MAX9163 toc01
DRIVER DIFFERENTIAL OUTPUT VOLTAGE vs. SUPPLY VOLTAGE
DRIVER DIFFERENTIAL OUTPUT VOLTAGE (mV)
MAX9163 toc02
DRIVER DIFFERENTIAL OUTPUT VOLTAGE vs. LOAD RESISTANCE
DRIVER DIFFERENTIAL OUTPUT VOLTAGE (V) 0.60 0.55 0.50 0.45 0.40 0.35 0.30 0.25 0.20 0.15 10 30 50 70 90 110 130
MAX9163 toc03
9.14 9.11 DRIVER DIFFERENTIAL OUTPUT SHORT-CIRCUIT CURRENT (mA) 9.08 9.05 9.02 8.99 8.96 8.93 8.90 3.0 3.1 3.2 3.3 3.4 3.5 DRIVER OUTPUTS SHORTED TOGETHER DIN = HIGH OR LOW
253 252 251 250 249 248 247 246
0.65
3.6
3.0
3.1
3.2
3.3
3.4
3.5
3.6
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
LOAD RESISTANCE ()
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5
Bus LVDS 3.3V Single Transceiver MAX9163
Typical Operating Characteristics (continued)
(VCC = 3.3V, FREQ = 100MHz, VID = 0.2V, VCM = 1.2V, RL = 27 1%, CL = 10pF, TA = +25C, unless otherwise noted.)
DRIVER SINGLE-ENDED OUTPUT SHORT-CIRCUIT CURRENT vs. SUPPLY VOLTAG
MAX9163 toc04
DRIVER SUPPLY CURRENT vs. FREQUENCY
MAX9163 toc05
SUPPLY CURRENT (ICC) vs. TEMPERATURE
13.32 SUPPLY CURRENT (mA) 13.30 13.28 13.26 13.24 13.22 13.20 DE = HIGH RE = LOW DC CURRENT -40 -15 10 35 60 85
MAX9163 toc06
9.09 DRIVER SINGLE-ENDED OUTPUT SHORT-CIRCUIT CURRENT (mA) 9.07 TO GND 9.05 9.03 9.01 8.99 DIN = HIGH OR LOW 8.97 3.0 3.1 3.2 3.3 3.4 3.5 TO VCC
30 DRIVER SUPPLY CURRENT (mA) 27 24 21 18 15 12
13.34
DE = HIGH RE = HIGH 0 25 50 75 100 125 150 175 200
13.18 13.16
3.6
SUPPLY VOLTAGE (V)
FREQUENCY (MHz)
TEMPERATURE (C)
DRIVER SUPPLY CURRENT (ICCD) vs. SUPPLY VOLTAGE
DRIVER DIFFERENTIAL PROPAGATION DELAY (ns)
MAX9163 toc07
DRIVER DIFFERENTIAL PROPAGATION DELAY vs. SUPPLY VOLTAGE
DRIVER DIFFERENTIAL PROPAGATION DELAY (ns)
MAX9163 toc08
DRIVER DIFFERENTIAL PROPAGATION DELAY vs. TEMPERATURE
3.8 3.6 3.4 3.2 3.0 2.8 2.6 2.4 2.2 -40 -15 10 35 60 85 TEMPERATURE (C) tPLHD tPHLD
MAX9163 toc09
13.6 DRIVER SUPPLY CURRENT (mA) 13.5 13.4 13.3 13.2 13.1 13.0 3.0 3.1 3.2 3.3 3.4 3.5 DE = HIGH RE = HIGH DC CURRENT
4.00 3.75 3.50 3.25 3.00 2.75 2.50 2.25 2.00 3.0 3.1 3.2 3.3 3.4 3.5 tPLHD tPHLD
4.0
3.6
3.6
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
DRIVER DIFFERENTIAL SKEW vs. SUPPLY VOLTAGE
MAX9163 toc10
DRIVER DIFFERENTIAL SKEW vs. TEMPERATURE
MAX9163 toc11
DRIVER TRANSITION TIME vs. SUPPLY VOLTAGE
MAX9163 toc12
0.23 DRIVER DIFFERENTIAL SKEW (ns) 0.22 0.21 0.20 0.19 0.18 0.17 3.0 3.1 3.2 3.3 3.4 3.5
0.40 DRIVER DIFFERENTIAL SKEW (ns) 0.35 0.30 0.25 0.20 0.15 0.10 0.05 0
1.2 1.0 tTLHD 0.8 0.6 0.4 0.2 0 tTHLD
3.6
-40
-15
10
35
60
DRIVER TRANSITION TIME (ns)
85
3.0
3.1
3.2
3.3
3.4
3.5
3.6
SUPPLY VOLTAGE (V)
TEMPERATURE (C)
SUPPLY VOLTAGE (V)
6
_______________________________________________________________________________________
Bus LVDS 3.3V Single Transceiver
Typical Operating Characteristics (continued)
(VCC = 3.3V, FREQ = 100MHz, VID = 0.2V, VCM = 1.2V, RL = 27 1%, CL = 10pF, TA = +25C, unless otherwise noted.)
MAX9163
DRIVER TRANSITION TIME vs. TEMPERATURE
MAX9163 toc13
DRIVER TRANSITION TIME vs. TOTAL LOCAL CAPACITANCE
RECEIVER OUTPUT SHORT-CIRCUIT CURRENT (mA)
MAX9163 toc14
RECEIVER OUTPUT SHORT-CIRCUIT CURRENT vs. SUPPLY VOLTAGE
35 30 25 20 15 10 5 VID = +100mV 0 3.0 3.1 3.2 3.3 3.4 3.5 3.6 SUPPLY VOLTAGE (V)
MAX9163 toc15
1.2 1.0 0.8 0.6 0.4 0.2 0 -40 -15 10 35 60
3.5 3.0 DRIVER TRANSITION TIME (ns) 2.5 2.0 1.5 tTHLD 1.0 0.5 0 tTLHD
40
DRIVER TRANSITION TIME (ns)
tTLHD
tTHLD
85
10
15
20
25
30
35
TEMPERATURE (C)
CAPACITANCE (pF)
RECEIVER OUTPUT HIGH VOLTAGE vs. SUPPLY VOLTAGE
MAX9163 toc16
RECEIVER OUTPUT LOW VOLTAGE vs. SUPPLY VOLTAGE
MAX9163 toc17
RECEIVER DIFFERENTIAL PROPAGATION DELAY vs. SUPPLY VOLTAGE
RECEIVER DIFFERENTIAL PROPAGATION DELAY (ns) 7.5 7.0 6.5 6.0 5.5 5.0 4.5 4.0 3.0 3.1 3.2 3.3 3.4 3.5 3.6 SUPPLY VOLTAGE (V) tPLH tPHL
MAX9163 toc18
3.7 RECEIVER OUTPUT HIGH VOLTAGE (V) 3.6 3.5 3.4 3.3 3.2 3.1 3.0 2.9 2.8 3.0 3.1 3.2 3.3 ILOAD = -40A VID = +100mV 3.4 3.5
0.030 RECEIVER OUTPUT LOW VOLTAGE (V)
8.0
0.028
0.026
0.024
0.022 ILOAD = 2mA VID = -100mV 3.0 3.1 3.2 3.3 3.4 3.5 3.6
0.020
3.6
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
RECEIVER DIFFERENTIAL PROPAGATION DELAY vs. TEMPERATURE
RECEIVER DIFFERENTIAL PROPAGATION DELAY (ns)
MAX9163 toc19
RECEIVER TRANSITION TIME vs. TOTAL LOAD CAPACITANCE
4.5 RECEIVER TRANSITION TIME (ns) 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 tTHL tTLH
MAX9163 toc20
8.0 7.5 7.0 6.5 6.0 5.5 tPLH 5.0 4.5 4.0 -40 -15 10 35 60 tPHL
5.0
85
0 10 15 20 25 30 35 CAPACITANCE (pF)
TEMPERATURE (C)
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7
Bus LVDS 3.3V Single Transceiver MAX9163
Pin Description
PIN 1 2 3 4 5 6 7 8 NAME DE DIN ROUT GND RE DO-/RIDO+/RI+ VCC FUNCTION LVTTL/LVCMOS Driver Enable Input. The driver is enabled when DE is high. When DE is low, the driver output is disabled and is high impedance. LVTTL/LVCMOS Driver Input LVTTL/LVCMOS Receiver Output Ground LVTTL/LVCMOS Receiver Enable Input. The receiver is enabled when RE is low. When RE is high, the receiver output is disabled and is high impedance. Inverting BLVDS Driver Output/Receiver Input Noninverting BLVDS Driver Output/Receiver Input Power-Supply Input. Bypass VCC to GND with 0.1F and 0.001F ceramic capacitors.
Detailed Description
The MAX9163 high-speed BLVDS transceiver is designed specifically for heavily loaded multipoint bus applications. The MAX9163 operates from a single 3.3V power supply, and is pin compatible with DS92LV010A. The transceiver consists of one differential BLVDS line driver and one LVDS receiver. The driver outputs and receiver inputs are connected internally to minimize bus loading. The driver and receiver can be enabled or disabled individually or simultaneously by the use of enable logic inputs (DE, RE). The MAX9163 driver output uses a current-steering configuration to generate a 9mA (typ) output current. This current-steering approach induces less ground bounce and no shoot-through current, enhancing noise margin and system speed performance. The outputs are short-circuit current limited. The MAX9163 currentsteering output requires a resistive load to terminate the signal and complete the transmission loop. With a typical 9mA output current, the MAX9163 produces a 243mV output voltage when driving a bus terminated with two 54 resistors (9mA x 27 = 243mV). The MAX9163 receiver detects a differential input as low as 100mV and translates it to a single-ended output. The device features an in-path fail-safe circuit that sets the receiver output high when the receiver inputs are undriven and open, terminated, or shorted.
input to ground, which drives the receiver output high. If the differential input is shorted or terminated with a typical value termination resistor, the +35mV offset drives the receiver output high. If the input is terminated and floating, the receiver output is driven high by the +35mV offset, and the 2:1 current sink to current source ratio (5A:2.5A) pulls the inputs to ground. This can be an advantage when switching between drivers on a multipoint bus. The change in common-mode voltage on the MAX9163 is from ground to the typical driver offset voltage of 1.2V. This is less than the change from VCC to 1.2V found on some circuits where the fail-safe circuitry pulls the bus to VCC.
Effects of Capacitive Loading
The characteristic impedance of a differential PC board trace is uniformly reduced when equal capacitive loads are attached at equal intervals (provided that the transition time of the signal being driven on the trace is longer than the delay between loads). This kind of loading is typical of multipoint buses where cards are attached at 1in or 0.8in intervals along the length of a backplane. The reduction in characteristic impedance is approximated by the following formula:
ZDF - loaded = ZDF - unloaded x [CO / (CO + (N x CL / L))]
Receiver In-Path Fail-Safe
The MAX9163 has in-path fail-safe circuitry, which is designed with a +35mV input offset voltage, a 2.5A current source between V CC and the noninverting input, and a 5A current sink between the inverting input and ground (Figure 6). If the differential input is open, the 2.5A current source pulls the input to about VCC - 0.7V and the 5A source sink pulls the inverting
8
where: Z DF-unloaded = unloaded differential characteristic impedance CO = unloaded trace capacitance (pF/unit length) CL = value of each capacitive load (pF) N = number of capacitive loads L = trace length
_______________________________________________________________________________________
Bus LVDS 3.3V Single Transceiver
For example, if CO = 2.5pF/in, CL = 10pF, N = 18, L = 18in, and ZDF-unloaded = 120, the loaded differential impedance is:
ZDF - loaded = 120 x
Applications Information
Power-Supply Bypassing
Bypass V CC with high-frequency, surface-mount ceramic 0.1F and 0.001F capacitors in parallel as close to the device as possible, with the smaller valued capacitor closest to VCC.
MAX9163
[2.5pF / (2.5pF + (18 x 10pF / 18in))]
where ZDF-loaded = 54
VCC 2.5A DO+/RI+ 35mV DO-/RI5A GND ROUT
Termination
In the example in the Effects of Capacitive Loading section, the loaded differential impedance of the bus is reduced to 54. Because the bus can be driven from any card position, it must be terminated at each end. A parallel termination of 54 at each end of the bus placed across the traces provides a proper termination. The total load seen by the driver is 27. In a multidrop bus where the driver is at one end and receivers are connected at regular intervals along the bus, the bus has lowered impedance due to capacitive loading. Assuming the same impedance as calculated in the multidrop example (54), the multidrop bus can be terminated with a single, parallel-connected 54 resistor at the far end of the driver. Only a single resistor is required because the driver sees one 54 differential trace. The signal swings are larger with a 54 load. In general, parallel terminate each end of the bus with a resistor matching the differential impedance of the bus (taking into account any reduced impedance due to loading).
MAX9163
Figure 6. Input Fail-Safe Circuit
In this example, capacitive loading reduces the characteristic impedance from 120 to 54. The load seen by a driver located on a card in the middle of the bus is 27 because the driver sees two 54 terminations in parallel. A typical LVDS driver (rated for a 100 load) would not develop a large enough differential signal to be detected reliably by an LVDS receiver. The MAX9163 BLVDS driver is designed and specified to drive a 27 load to differential voltage levels of 180mV to 360mV. A standard LVDS receiver is able to detect this level of differential signal. Short extensions off the bus, called stubs, contribute to capacitive loading. Keep stubs less than 1in for a good balance between ease of component placement and good signal integrity. The MAX9163 driver outputs are current-source drivers and drive larger differential signal levels into resistances higher than 27 and smaller levels into resistances lower than 27 (see the Typical Operating Characteristics curves). To keep loading from reducing bus impedance below the rated 27 load, PC board traces can be designed for higher unloaded characteristic impedances.
Traces, Cables, and Connectors
The characteristics of differential input and output connections affect the performance of the device. Use controlled-impedance traces, cables, and connectors with matched characteristic impedance. Ensure that noise couples as common mode by running the traces of a differential pair close together. Reduce within-pair skew by matching the electrical length of the conductors within a differential pair. Excessive skew can result in a degradation of magnetic field cancellation. Maintain the distance between conductors within a differential pair to avoid discontinuities in differential impedance. Minimize the number of vias to further prevent impedance discontinuities.
Board Layout
For BLVDS applications, a four-layer PC board with separate power, ground, BLVDS, LVDS, and logic signal layers is recommended. Separate the LVTTL/ LVCMOS and BLVDS signals to prevent coupling.
Power-On Reset
The power-on reset voltage of the MAX9163 is typically 2.2V. When the supply falls below this voltage, the device is disabled and the outputs (DO+/RO+, DO-/RO-, and ROUT) are high impedance.
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9
Bus LVDS 3.3V Single Transceiver MAX9163
Typical Application Circuit
MAX9163
DIN/ROUT
MAX9163
DIN/ROUT
MAX9163
DIN/ROUT
54
54
DIN/ROUT
DIN/ROUT
DIN/ROUT
MAX9163
TABLE 1. FUNCTION SELECT DE H L L H RE H L H L MODE SELECTED Driver Receiver High impedance Loopback
MAX9163
MAX9163
TABLE 3. RECEIVER MODE INPUTS (DO+/RI+) - (DO-/RI-) RE L ( -100mV) L H ( 100mV) L (> -100mV and < 100mV) L Undriven and open, shorted, L or terminated X H DE: Low X: High or low Z: High impedance
TABLE 2. DRIVER MODE INPUTS OUTPUTS DE DIN DO+/RI+ DO-/RIH L ( 0.8V) L H H H ( 2.0V) H L H (> 0.8mV and < 2.0mV) Undefined Undefined L X Z Z X: High or low Z: High impedance
OUTPUT ROUT L H Undefined H Z
Chip Information
TRANSISTOR COUNT: 901 PROCESS: CMOS
10
______________________________________________________________________________________
Bus LVDS 3.3V Single Transceiver
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
SOICN .EPS
MAX9163
INCHES DIM A A1 B C e E H L MAX MIN 0.069 0.053 0.010 0.004 0.014 0.019 0.007 0.010 0.050 BSC 0.150 0.157 0.228 0.244 0.016 0.050
MILLIMETERS MAX MIN 1.35 1.75 0.10 0.25 0.35 0.49 0.19 0.25 1.27 BSC 3.80 4.00 5.80 6.20 0.40 1.27
N
E
H
VARIATIONS:
1
INCHES
MILLIMETERS MIN 4.80 8.55 9.80 MAX 5.00 8.75 10.00 N MS012 8 AA 14 AB 16 AC
TOP VIEW
DIM D D D
MIN 0.189 0.337 0.386
MAX 0.197 0.344 0.394
D C
A e B A1
0 -8 L
FRONT VIEW
SIDE VIEW
PROPRIETARY INFORMATION TITLE:
PACKAGE OUTLINE, .150" SOIC
APPROVAL DOCUMENT CONTROL NO. REV.
21-0041
B
1 1
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 11 (c) 2003 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

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